VLSI Design of Dual-Mode Double Precision Floating Point Division with Reduced Area

Asiya. Shaik, P. Jaya Rami Reddy .


Floating point division is a core arithmetic widely used in scientific and engineering applications. This paper proposed an architecture for double precision floating point division. This architecture is designed for dual-mode functionality, which can either compute on a pair of double precision operands or on two pairs of single precision operands in parallel. The architecture is based on the series expansion multiplicative methodology of mantissa computation. For this, a novel dualmodeRadix-4 Modified Booth multiplier is designed, which is used iteratively in the architecture of dual-mode mantissa computation. Other key components of floating point division flow (such as leading-one-detection, left/right dynamic shifters, rounding, etc.) are also re-designed for the dual-mode operation. The proposed dual-mode architecture is synthesized using Xilinx14.7technology. Two versions of proposed architecture are presented, one with single stage multiplier and another with two stage multiplier.

Full Text:



J.-C. Jeong, W.-C. Park, W. Jeong, T.-D. Han, and M.-K. Lee, “A costeffectivepipelined divider with a small lookup table,” IEEE Trans.Comput., vol. 53, no. 4, pp. 489–495, Apr. 2004.

S. F. Oberman and M. Flynn, “Division algorithms and implementations,”IEEE Trans. Comput., vol. 46, no. 8, pp. 833–854, Aug. 1997.

M. K. Jaiswal and R. C. C. Cheung, “High performance reconfigurablearchitecture for double precision floating point division,” in Proc. 8thInt. Symp. Appl. Reconfigurable Comput. (ARC), Hong Kong, China,Mar. 2012, pp. 302–313.

X. Wang and M. Leeser, “VFloat: A variable precision fixed- andfloating-point library for reconfigurable hardware,” ACM Trans. ReconfigurableTechnol. Syst., vol. 3, no. 3, pp. 16:1–16:34, Sep. 2010.

M. K. Jaiswal, R. Cheung, M. Balakrishnan, and K. Paul, “Seriesexpansion based efficient architectures for double precision floating pointdivision,” Circuits, Syst., Signal Process., vol. 33, no. 11, pp. 3499–3526,2014. [Online]. Available: http://dx.doi.org/10.1007/s00034-014-9811-8

J.-M. Muller et al., Handbook of Floating-Point Arithmetic, 1st ed.Basel, Switzerland: Birkhäuser, 2009.

P. Soderquist and M. Leeser, “Area and performance tradeoffs infloating-point divide and square-root implementations,” ACM Comput.Surv., vol. 28, no. 3, pp. 518–564, Sep. 1996.

B. Parhami, Computer Arithmetic: Algorithms and Hardware Designs,2nd ed. New York, NY, USA: Oxford Univ. Press, 2010.

B. Pasca, “Correctly rounded floating-point division for DSP-enabledFPGAs,” in Proc. 22nd Int. Conf. Field Program. Logic Appl. (FPL),Aug. 2012, pp. 249–254.

A. Akka¸s, “Dual-mode quadruple precision floating-point adder,” inProc. Euromicro Symp. Digit. Syst. Design, 2006, pp. 211–220.

M. Ozbilen and M. Gok, “A multi-precision floating-point adder,”in Proc. Ph.D. Res. Microelectron. Electron. (PRIME), 2008,pp. 117–120.

M. K. Jaiswal, R. C. C. Cheung, M. Balakrishnan, and K. Paul,“Unified architecture for double/two-parallel single precision floatingpoint adder,” IEEE Trans. Circuits Syst. II, Express Briefs, vol. 61, no. 7,pp. 521–525, Jul. 2014.

A. Akka¸s, “Dual-mode floating-point adder architectures,” J. Syst. Archit., vol. 54, no. 12, pp. 1129–1142, Dec. 2008.

M. Jaiswal, B. Varma, H.-H. So, M. Balakrishnan, K. Paul, andR. Cheung, “Configurable architectures for multi-mode floating pointadders,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 62, no. 8,pp. 2079–2090, Aug. 2015.

A. Baluni, F. Merchant, S. K. Nandy, and S. Balakrishnan, “A fullypipelined modular multiple precision floating point multiplier withvectorsupport,” in Proc. Int. Symp. Electron. Syst. Design (ISED), 2011,pp. 45–50.

DOI: https://doi.org/10.23956/ijarcsse.v8i6.740


  • There are currently no refbacks.

© International Journals of Advanced Research in Computer Science and Software Engineering (IJARCSSE)| All Rights Reserved | Powered by Advance Academic Publisher.