VLSI Design of Carry Select Adder Using Redundant Encoding Technique for Arithmetic Calculations

P. Lokesh, K. Mandal .

Abstract


Carry Select Adder (CSLA) is one of the best adders used in many data-processing processors to perform fast arithmetic functions. From the structure of the CSLA, it is obvious that there is possibility for reducing the area and power consumption in the CSLA. CSLA is used in numerous computational systems to ease the problem of carry propagation delay by autonomously generating multiple carries and then select a carry to produce the sum. However, the CSLA is not area competent because it uses several pairs of Ripple Carry Adders (RCA) to generate partial sum and carry by in view of carry input Cin=0 and Cin=1, then the final sum and carry are selected by the multiplexers. Due to the fast growing mobile industry not only the faster arithmetic unit but also less area and low power arithmetic units are needed. Since the CSLA suffering with Redundancy problem this paper presented a novel technique to eliminate all the redundant logic operations present in the traditional CSLA and proposed a new logic formulation for CSLA. In the proposed scheme, the carry select (CS) operation is scheduled before the calculation of final-sum, which is unlike from the conventional approach. Bit patterns of two anticipating carry words (corresponding to Cin = 0 and 1) and fixed Cin bits are used for logic optimization of CS and generation units. An efficient CSLA design is obtained using optimized logic units. The proposed CSLA design involves considerably less area and delay than the recently proposed BEC-based CSLA. Due to the small carry-output delay, the proposed CSLA design is a good entrant for square-root (SQRT) CSLA. The proposed design is simulated, synthesized and verified by Xilinx tools along with Virtex – 5 FPGA board.

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References


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