VLSI Design of Dual-Mode Double Precision Floating Point Division with Reduced Area

Asiya. Shaik, P. Jaya Rami Reddy .

Abstract


Floating point division is a core arithmetic widely used in scientific and engineering applications. This paper proposed an architecture for double precision floating point division. This architecture is designed for dual-mode functionality, which can either compute on a pair of double precision operands or on two pairs of single precision operands in parallel. The architecture is based on the series expansion multiplicative methodology of mantissa computation. For this, a novel dualmodeRadix-4 Modified Booth multiplier is designed, which is used iteratively in the architecture of dual-mode mantissa computation. Other key components of floating point division flow (such as leading-one-detection, left/right dynamic shifters, rounding, etc.) are also re-designed for the dual-mode operation. The proposed dual-mode architecture is synthesized using Xilinx14.7technology. Two versions of proposed architecture are presented, one with single stage multiplier and another with two stage multiplier.

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References


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DOI: https://doi.org/10.23956/ijarcsse.v8i6.740

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